1. Field of the Invention
The present invention relates to a semiconductor device capable of improving a breakdown voltage on a thin insulating film formed between poly-Si layers, and to a method for manufacturing the same.
2. Description of the Related Art
Known in a semiconductor device of a type which is manufactured by forming a poly-Si film on an insulating film overlying a major surface of a semiconductor substrate, forming an insulating film on the poly-Si film and forming a poly-Si layer, these poly-Si films being employed as an electrode.
An EPROM is known as this type of a semiconductor device. FIG. 1 is a cross-sectional view showing one of manufacturing steps of a conventional EPROM. In FIG. 1 , first thermal oxide film 2 of 500 .ANG. in thickness and field oxide film are formed over the surface of P.sup.- type silicon substrate 1, the field oxide film surrounding an element area. First poly-Si layer 3 of 1000 .ANG. in thickness, which is used as a floating gate electrode formation layer, is formed by means of a low-pressure chemical vapor deposition (CVD) method on field oxide film 1 and on first thermal oxide film 2.
Phosphorus are doped by means of a thermal diffusion method into first poly-Si silicon film 3. The surface of first poly-Si film 3 is thermally oxidized at about 1000.degree. C., thereby forming second thermal oxide film 4 having a thickness of 500 .ANG..
Second poly-Si film 5 for control gate electrode formation is formed on the surface of a resultant structure by means of a low-pressure CVD method. Phosphorus are doped by means of a thermal diffusion method into second poly-Si film 5.
FIG. 2 is a cross-sectional view showing a model of a conventional EPROM. An explanation will be given below of the process for manufacturing a conventional EPROM, by referring to FIGS. 1 and 2 (a complete view).
Second poly-Si film 5, second thermal oxide film 4, first poly-Si film 3 and first thermal oxidation film 2 are sequentially etched by means of a photoetching method. As a result, control gate electrode 15, second gate oxide film 14, floating gate electrode 13 and first gate oxide film 12 are formed in the semiconductor structure as shown in FIG. 2.
Then an N-type impurity is ion-implanted into a surface portions of the semiconductor structure 1 using control gate electrode 15, second gate oxide film 14, floating gate electrode 13 and first gate oxide film 12 as masks. Substrate 1 is heat-treated, thereby diffusing the N-type impurity deep into substrate 1. As a result, N.sup.+ type drain region 16 and N.sup.+ type source region 17 are formed in the semiconductor substrate.
The surface of the resultant structure is thermally oxidized to provide thermal oxide film 18 with which the surfaces of substrate 1 and control gate electrode 15, as well as the side surfaces of second gate oxide film 14, floating gate electrode 14 and first oxide film, are surrounded.
Passivation layer 19, such as a PSG film, is deposited on the whole surface of the resultant surface.
Passivation layer 19 is selectively etched to form contact holes. As a result, the portions of drain region 16 and source region 17 are exposed at the locations of the contact holes. An A(-Si layer is deposited wholly on the surface of the resultant structure, followed by a patterning step to provide drain electrode 20 and source electrode 21. In this way, a conventional EPROM is completed as shown in FIG. 2.
The EPROM is of such a type that it allows the writing of data by the application of a high positive voltage across N.sup.+ type drain region 16 and control gate electrode 15 and the injection of electrons into floating gate electrode 13.
It is necessary that electrons injected into floating gate electrode 13 be stored in floating gate electrode 13 for a prolonged period of time.
There are cases where, if any high positive voltage is applied to control gate electrode 15 for some accidental reason or other, the electrons thus stored in floating gate electrode 13 are absorbed via second gate oxide film 14 and data is dissipated. This phenomenon that, when a high voltage is applied to control gate electrode 15, electrons stored in floating gate electrode 13 are absorbed via second gate oxide film 14 into control gate electrode 15 is believed to be caused by the following reason.
After deposition of poly-Si film 3 for the formation of floating gate electrode 13, phosphorus are doped by the thermal diffusion into first poly-Si silicon film 3 and the surface of first poly-Si film 3 is thermally oxidized to provide second thermal oxide film 4 as second gate oxide film 14.
After the deposition of second poly-Si film 5 for the formation of control gate electrode 15, phosphorus are doped by a thermal diffusion method into second poly-Si film 5.
Then various thermal treatments are performed at the steps including the formation of thermal oxide film 18.
Phosphorus are doped into first poly-Si film 3 and second poly-Si film 5 and migrated toward first thermal oxide film 2 and second thermal oxide film 4, respectively.
As a result, a phosphorus concentration profile in first poly-Si film 3 and second poly-Si film 5 is as shown in FIG. 3. That is, the phosphorus concentration becomes higher at the outer edge portions A and C of first poly-Si film 3 and second poly-Si film 5.
This means that the phosphorus are diffused into first thermal oxide film 2 and second thermal oxide film 4. As a result, the close density of first thermal oxide film 2 and second thermal oxide film 4 is reduced to reveal the electrical conductivity. The breakdown voltage is thus reduced, permitting the ready electron migration.
When a high voltage is applied to control gate electrode 15, electrons stored in floating gate electrode 13 is absorbed in control gate electrode 15 via second gate oxide film 14.